The occurrence ratio of electro-static discharge (ESD) in large-scale display panel development is rather high, and there is no definite solution for defects caused by ESD. It is found by investigation that a crucial reason for the frequent occurrence of ESD defects is the common electrode line fabricated at the same time as the gate layer. Since charges may easily gather on a large area metal sheet, local electric fields tend to be uneven under a plasma environment such as in a Plasma Enhanced Chemical Vapor Deposition (PECVD) device, which may easily cause tip discharge, thereby leading to ESD in different metal layers or electrostatic breakdown.
In conventional technologies, common electrode metal at the periphery of the display region is normally designed as an integral plate, such that the common electrode in the display region of the display panel has a uniform voltage distribution. However, such a design may generate local potential differences, which will cause tip discharge with too large electrostatic energy and easily form ESD defects or electrostatic breakdown.